1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing techniques for copper metallization , and in particular, to a method for forming barrier layer for copper metallization.
2. Description of the Prior Art
Heretofore, in general, aluminum wirings have been being used in LSI. Copper wirings are being developed in the art as low-resistance metal wirings having higher electric conductivity and reliability over Al wirings. The specific resistivity of copper is around 1.8 .mu..OMEGA..multidot.cm or so, while that of aluminum is around 2.9 .mu..OMEGA..multidot.cm or so, and it is expected that copper wirings will bring about the reduction in electric resistance of around 40% or so, when compared with aluminum wirings.
However, in realizing copper wirings, there are many difficulties that must be overcome with respect to the process for forming them. Still now, therefore, aluminum is the mainstream of the wiring material for LSI from the birth of LSI where aluminum was first used for wirings.
Essential problems with the process of forming copper wirings are as follows: The first is that copper RIE (reactive ion etching) is difficult to attain and therefore copper wiring patterns are difficult to form. The second is that copper diffuses through interlayer insulating films (silicon oxide films) due to heat and electric field, thereby often having some negative influences on the other devices in LSI and causing electric leak through wirings therein. The third is that copper is easily oxidized in an oxidizing process to form an oxide film. Since the oxide film is thick and its mechanical and chemical strength is low, it interferes with the formation of good copper wirings.
The first problem could be solved by a technique of embedding a metal in grooves (in a so-called damascene-wiring process) with no RIE to form wiring patterns. On the other hand, the second and third problems could be solved by covering the wiring patterns with a barrier material (conductor, insulator)
As in FIG. 1, barrier layer 13 is formed around the inner surface of each damascene groove as formed in an interlayer insulating film 12 on a semiconductor substrate 11, whereby the bottom and the side surface of copper wiring 14 could be covered with the barrier layer 13. However, in this, any other method must be employed for forming barrier layer to cover the top of the copper wiring 14. For this, some methods have heretofore been proposed, such as those mentioned below.
The first method comprises forming copper wiring 14 followed by covering the entire surface with an insulating barrier layer 61 of, for example SiN, as in FIG. 2. The second method comprises forming copper wiring 14 followed by forming a barrier metal layer 71 selectively on the copper wiring 14 through electroless plating or selective metal CVD, as in FIG. 3. The third method comprises, as in FIGS. 4A to 4C, forming barrier layer 13 and copper wiring 14 in each damascene groove (FIG. 4A), then etching (o recessing) the copper wiring 14 and forming barrier layer 81 on the entire surface by the use of ,e.g. sputtering or CVD method (FIG. 4B), and finally embedding the barrier layer 81 in the etched recesses by the use of ,e.g. chemical mechanical polishing method according to a damascene process (FIG. 4C).
However, the first method is problematic in that the capacitance between the wirings is increased due to the SiN film 61 formed on the interlayer insulating film 12 around the copper wiring 14 and having a high dielectric constant, thereby lowering the acting speed of LSI. The second method is problematic in that the selective formation of the barrier layer is difficult to control and therefore the short-circuit margin between the wirings is low, and that a chloride or a chlorine formed in WCVD corrodes the copper wiring 14. In the third method, the structure formed is such that the barrier layer is embedded in the site in which the recesses are formed,the thickness of the interlayer insulating film in that structure must be increased according to the thickness of the barrier layer. As a result, therefore, the third method is problematic in that the process controllability in the direction of thickness is not good.
Takewaki, et al. say that SiH.sub.4 gas decomposes and Si deposits on Copper interconnect surface in the temperature range of 150.degree. C..about.400.degree. C. (T. Takewaki, et al., A Novel Self-Aligned Surface-Silicide Passivation Technology for Reliability Enhancement in Copper Interconnections, 1995 Symposium on VLSI Technology). On the basis of that phenomenon, Takewaki, et al. tried forming a copper silicide on the surface of copper wirings to improve the reliability of the wirings. However, their proposal is problematic in that the copper silicide could not satisfactorily function as a film for preventing copper diffusion or oxidation.
Even though hopeful for low-resistance metal wirings, copper is still problematic in that it diffuses through interlayer insulating films and is easily oxidized in an oxidation process to form an oxide film having low mechanical and chemical strength. Therefore, as so mentioned hereinabove, forming barrier layer around copper wirings is indispensable. However, the conventional barrier layer-forming methods are problematic in that the capacitance in the wirings formed is increased and that the barrier layer formed could not satisfactorily function as a film for preventing copper diffusion or oxidation.